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Cadence heard you wanted some AI in your AI so it used AI to design an AI chip (www.theregister.com)

submitted 1 day ago by tonytins@pawb.social to c/nottheonion@lemmy.world

18 comments fedilink hide all child comments

The idea of machines that can build even better machines sounds like sci-fi, but the concept is becoming a reality as companies like Cadence tap into generative AI to design and validate next-gen processors that also use AI.

In the early days of integrated circuits, chips were designed by hand. In the more than half a century since then, semiconductors have grown so complex and their physical features so small that it's only possible to design chips using other chips. Cadence is one of several electronic design automation (EDA) vendors building software for this purpose.

Even with this software, the process of designing chips remains time-consuming and error-prone. But with the rise of generative AI, Cadence and others have begun exploring new ways to automate these processes.

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[–] gravitas_deficiency@sh.itjust.works 7 points 17 hours ago* (last edited 17 hours ago) (1 children)

In the realm of advanced chip design, you need deterministic algorithms to validate chip design. Literally any amount of hallucination in that process is going to result in an unbelievable amount of wasted resources, because setting up a chip fab for a particular design is mind-rendingly complex. You have to worry about things like how to etch features in silicon that are smaller by an order of magnitude than the wavelength of the light that you’re using to etch the features. And that’s just one of the insanely difficult problems that make the process so difficult to make reliable. You know those stats you see about poor chip yields? That and problems like it are the source - and that’s without accounting for design errors, which, while generally far less common, are far from unheard of (coughINTELcough).

[–] CheeseNoodle@lemmy.world 3 points 17 hours ago

This is what I was thinking (but you seem way smarter than me) the design of a chip is about as close to pure math as a physical object can get so in order to validate it we're going to use software that's just math but worse?