this post was submitted on 23 Oct 2024
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What do you mean by standards?
Several differing extensions of the RISC-V core machine instructions, for example. A pain in the rear for any compiler builder.
That’s a good thing, meaning you can design RISC-V CPUs without functionality you don’t need (like microcontrollers that only need basic operations). However, for those who want a complete CPU, there are RVA profiles (latest being RVA23), which are a list of extensions required to be an application-ready CPU. So there’s really just 1 “standard” for general purpose computing, everything else is for specialized products.
And it does not concern you that this RVA profile is version 23? Which means there are a number of CPUs based on lower versions, too, as they don't just update on a whim? And they are incompatible, with version 23 because they lack instructions?
So a compiler would have to support at least a certain number of those profiles (usually, parts in the embedded world are supported for 10+ years!), and be capable of supporting the one or other non-RVA extension, too, to satisfy customer needs.
That is exactly what I meant with "too many standards".
Not sure where you got that information. There are only 5 RISC-V profiles.
Like all the x86 CPUs from a few years ago that don’t have all the new extensions? Not supporting new extensions doesn’t mean the CPU is useless, only that it’s worse than new ones, as things should be when there’s progress. Or I guess you throw out your x86 CPU every time Intel/AMD create a new instruction?
Do you think compilers only target one x86 version with one set of instructions? For example in x86, there’s SIMD versions SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, SSE4.2, compilers support all of them, and that’s literally just for the SIMD instructions. What’s new?
Yes, there are differences in certain x86 command sets. But they actually have a market. RISC-V is just a niche, and splintering in a small niche is making the support situation worse.
The support situation is so bad that both GCC and LLVM have extensive for RISC-V.