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RISC-V is sloooow – Marcin Juszkiewicz [Perspective from a Fedora developer]
(marcin.juszkiewicz.com.pl)
this post was submitted on 14 Mar 2026
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Hardware
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ISA. API exist at a different level. But basically sure. The ISA specifies how instructions should behave. But it's up to the chip designer to figure out how to accomplish it. Its the difference between HTML and Chrome or Firefox. They both take HTML instructions and use them to present the page as desired. But could get there very differently.
A lot of processor "speed" increase since the 2010s has come from parallelization and SIMD etcetera. Most of the Risc-v cores and SoC to this point have been micro controller or basic proof of concept cores for development. With speeds and performance matching early 2000s systems. But the newer RVA23 systems coming out should mark the start of the more specialized and powerful application processors. But implementation will always play a factor.
Exactly, which is my point, and since RISC-V doesn't have a specific chip designer, but the ISA is open, you can't equal RISC-V ISA in general to any specific chip.
Yes, it would technically be like defining AMD to mean all x86 architecture. Sometimes it would have reflected well. Other times not. But never would have been accurate.
Hopefully though well see smart SIMD subsystems and vector units that can accelerate the operations. Without requiring new hard coded CISC microcode like modern x86. But only time will tell.