What you wish for is how I use make. Off the top of my head, something like this:
EXEC = programname
SOURCES = $(wildcard *.c)
OBJECTS = $(SOURCES:.c=.o)
all: $(EXEC)
$(EXEC): $(OBJECTS)
%.o: %.c %.h
.PHONY: all clean
clean:
rm -f $(EXEC) $(OBJECTS)
Then just run make and it compiles and links all .c files into the executable. Each .c file needs a .h with the same name. Remove the %.h if you don't like that requirement.
From memory you might need a .c and .h file with the same name as the executable.