Gowin FPGA synthesis stuck on 95% (lemmy.world)

submitted 10 months ago by original2@lemmy.world to c/askelectronics@discuss.tchncs.de

0 comments fedilink hide all child comments

I am making a graphics card on the tang nano 20k board. I tried synthesising the design in the official IDE and it output:

[95%] Generate netlist file "/home/original2/Downloads/Gowin_V1.9.8.09_Education_linux/IDE/bin/VGA_out/impl/gwsynthesis/VGA_out.vg" completed

with no further updates for 40 minutes so far. I am on a 16 core system with 24GB of ram (the process is maxing out 1 core right now as well as using 6GB RAM). Why is it not progressing..

I do have a 60 by 80 array with 11 bit numbers in it if that is relevant

no comments (yet)

sorted by: hot top controversial new old

there doesn't seem to be anything here

this post was submitted on 24 Aug 2023

4 points (100.0% liked)

Ask Electronics

3139 readers

1 users here now

For questions about component-level electronic circuits, tools and equipment.

Rules

1: Be nice.

2: Be on-topic (eg: Electronic, not electrical).

3: No commercial stuff, buying, selling or valuations.

4: Be safe.

founded 1 year ago

MODERATORS

DavideAndrea@discuss.tchncs.de

linker3000@discuss.tchncs.de