So these people have been out here since earlier this year with this idea, and I think they raised a bit of money. There are a few problems that make me immediately hesitant to believe this is useful at all though:

1. they have been incredibly vague about they intend this to work
2. they've said they've shipped this around already, and are still looking for a partner to test with
3. whatever the solution actually, it's not a drop in
4. it would not only require a custom compiler, but a rewrite of any existing software
5. it's process-oriented and can't be patented (at least in the states), so any chip maker could just take the idea and do their own implementation

Best possible case is that it works, and their compiler and tooling can help with simplified refactoring of code, making that part the actual product that makes them a useful company.

Worst case is it's a total BS idea. Hesitant to say anything like that until we hear what the downsides are from a tested proof of concept

Whatever the outcome, it just isn't that big of a draw when you're thinking about very specific workloads that can function in this type of parallelism. As they've already mentioned, they've mocked this on an FPGA, so why wouldn't devs just build and run this specific work on something like AMD's FPGA chips in a DC setting and get even 75% of the way there?

I dont feel most really need faster. But everyone needs more power efficient chips.

Hopefully this turns out to deliver both.

I love how you just smashed together the title and the subtitle together to make something wholly confusing